Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling. As the semiconductor industry moves towards the 7-nm technology node and beyond, semiconductor FET device structures must be scaled to smaller dimensions to provide increased device width per footprint area. In this regard, non-planar FET devices such as nanosheet FET devices, nanowire FET devices, vertical FET devices, FinFET devices, etc., are a viable option for continued CMOS scaling. In general, a nanowire FET device comprises a device channel which comprises one or more nanowire layers in a stacked configuration, wherein each nanowire comprises an elongated semiconductor layer that has a width which is substantially the same or slightly larger than a thickness of the elongated semiconductor layer. A nanosheet FET device is similar to a nanowire FET device sheet in that a device channel comprises one or more nanosheet layers in a stacked configuration, but wherein each nanosheet layer has a width which is substantially greater than a thickness of the nanosheet layer. In nanowire/nanosheet FET devices, a common gate structure is formed above and below each nanowire/nanosheet layer in the stacked configuration, thereby increasing the FET device width (or channel width), and thus the drive current, for a given footprint area.
One issue with nanosheet FET devices is gate resistance. Given the small gate length, after removing a dummy gate structure and depositing high-k gate dielectric and work function metal (WFM) in the gate opening, there is not much room left for a low resistance gate metal. This is particularly problematic with nanosheet CMOS with different WFMs. Indeed, at least some nanosheet FETs will have two WFMs in the gate opening, wherein one is for threshold voltage (Vt) control and the other is a result of multiple WFM patterning. WFM chamfering techniques can be utilized to partially remove WFM above the nanosheet stack. However, conventional WFM chamfering techniques require recessing the WFM metal directly or recessing a sacrificial material (e.g., organic planarizing layer) in the gate region, and then removing the exposed WFM. This recess is performed by timed etch, whereby the recess must be carefully controlled to ensure that enough WFM remains on an upper nanosheet layer (or active channel) at of the nanosheet stack. Otherwise, the WFM could be completely removed from the upper nanosheet layer, which adversely impacts the electrical characteristics of the upper nanosheet layer of the nanosheet stack and introduces device variability in the nanosheet FET devices.